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Dr Themis Prodromakis

University of Southampton
Nano Group, Southampton Nanofabrication Centre
Southampton, SO17 1BJ, UK
+44 (0)23 8059 8803

A 1.5ns OFF/ON Switching-Time Voltage-Mode LVDS Driver/Receiver Pair for Asynchronous AER Bit-Serial Chip Grid Links with up to 40 Times Event-Rate Dependent Power Savings

Authors: C. Zamarreño-Ramos, R. Kulkarni, J. Silva-Martínez, T. Serrano-Gotarredona, and B. Linares-Barranco

Published by: IEEE Transactions on Biomedical Circuits and Systems

This paper presents a low power fast ON/OFF switchable voltage mode implementation of a driver/receiver pair intended to be used in high speed bit-serial LVDS (Low Voltage Differential Signaling) AER (Address Event Representation) chip grids, where short (like 32-bit) sparse data packages are transmitted.
Voltage-Mode drivers require intrinsically half the power of their Current-Mode counterparts and do not require Common-Mode Voltage Control. However, for fast ON/OFF switching a special high-speed voltage regulator is required which needs to be kept ON during data pauses, and hence its power consumption must be minimized, resulting in tight design constraints.
A proof-of-concept chip test prototype has been designed and fabricated in low-cost standard 0.35um CMOS.
At +/-500mV voltage swing with 500Mbps serial bit rate and 32 bit events, current consumption scales from 15.9mA (7.7mA for the driver and 8.2mA for the receiver) at 10Mevent/s rate to 406uA (343uA for the driver and 62.5uA for the receiver) for an event rate below 10Kevent/s, therefore achieving a rate dependent power saving of up to 40 times, while keeping switching times at 1.5ns.
Maximum achievable event rate was 13.7Meps at 638Mbps serial bit rate.
Additionally, differential voltage swing is tunable, thus allowing further power reductions.

Funding Research Councils:
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